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? 2003 microchip technology inc. preliminary ds21673c-page 1 24aa515/24lc515/24FC515 device selection table features ? low-power cmos technology - maximum write current 3 ma at 5.5v - maximum read current 400 a at 5.5v - standby current 100 na typical at 5.5v 2-wire serial interface bus, i 2 c ? compatible cascadable for up to four devices self-timed erase/write cycle 64-byte page write mode available 5 ms max write cycle time hardware write-protect for entire array output slope control to eliminate ground bounce schmitt trigger inputs for noise suppression 100,000 erase/write cycles electrostatic discharge protection > 4000v data retention > 200 years 8-pin pdip, soic packages temperature ranges: description the microchip technology inc. 24aa515/24lc515/ 24FC515 (24xx515*) is a 64k x 8 (512k bit) serial electrically erasable prom, capable of operation across a broad voltage range (1.8v to 5.5v). it has been developed for advanced, low power applications such as personal communications or data acquisition. this device has both byte write and page write capabil- ity of up to 64 bytes of data. this device is capable of both random and sequential reads. reads may be sequential within address boundaries 0000h to 7fffh & 8000h to ffffh. functional address lines allow up to four devices on the same data bus. this allows for up to 2 mbits total system eeprom memory. this device is available in the standard 8-pin plastic dip and soic packages. package type block diagram part number v cc range max clock frequency temp ranges 24aa515 1.8-5.5v 400 khz ? i 24lc515 2.5-5.5v 400 khz i 24FC515 2.5-5.5v 1 mhz i ? 100 khz for v cc < 2.5v. - industrial (i): -40 cto +85 c a0 a1 a2 v ss v cc wp scl sda 1 2 3 4 8 7 6 5 24aa515/ pdip soic a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda 24aa515/ hv generator eeprom array page latches ydec xdec sense amp r/w control memory control logic i/o control logic i/o a0 a1 sda scl v cc v ss wp 512k i 2 c ? cmos serial eeprom 24xx515 is used in this docum ent as a generic part number for the 24aa515/24lc515/24FC515 devices.
24aa515/24lc515/24FC515 ds21673c-page 2 preliminary ? 2003 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .......-65c to +125c esd protection on all pins ............................................................................................................................... ....................... 4kv table 1-1: dc characteristics ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c param. no. sym characteristic min max units conditions d1 a0, a1, scl, sda, and wp pins: d2 v ih high-level input voltage 0.7 v cc ?vv cc 2.5v d3 v il low-level input voltage ? 0.3 v cc 0.2 v cc v v v cc 2.5v v cc < 2.5v d4 v hys hysteresis of schmitt trigger inputs (sda, scl pins) 0.05 v cc ?vv cc 2.5v (note) d5 v ol low-level output voltage ? 0.40 v i ol = 3.0 ma @ v cc = 4.5v i ol = 2.1 ma @ v cc = 2.5v d6 i li input leakage current ? 1 av in = v ss or v cc , wp = v ss v in = v ss or v cc , wp = v cc d7 i lo output leakage current ? 1 av out = v ss or v cc d8 c in , c out pin capacitance (all inputs/outputs) ?10pfv cc = 5.0v (note) t a = 25c, f c = 1 mhz d9 i cc read operating current ? 400 av cc = 5.5v, scl = 400 khz i cc write ? 3 ma v cc = 5.5v d10 iccs standby current ? 5 a scl = sda = v cc = 5.5v a0, a1, wp = v ss , a2 = v cc note: this parameter is periodically sampled and not 100% tested.
? 2003 microchip technology inc. preliminary ds21673c-page 3 24aa515/24lc515/24FC515 table 1-2: ac characteristics ac characteristics industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c param. no. sym characteristic min. max. units conditions 1f clk clock frequency ? ? ? 100 400 1000 khz 1.8v v cc 2.5v 2.5v v cc 5.5v 2.5v v cc 5.5v (24FC515 only) 2t high clock high time 4000 600 500 ? ? ? ns 1.8v v cc 2.5v 2.5v v cc 5.5v 2.5v v cc 5.5v (24FC515 only) 3t low clock low time 4700 1300 500 ? ? ? ns 1.8v v cc 2.5v 2.5v v cc 5.5v 2.5v v cc 5.5v (24FC515 only) 4t r sda and scl rise time (note 1) ? ? ? 1000 300 300 ns 1.8v v cc 2.5v 2.5v v cc 5.5v 2.5v v cc 5.5v (24FC515 only) 5t f sda and scl fall time (note 1) ? ? 300 100 ns all except, 24FC515 2.5v v cc 5.5v (24FC515 only) 6t hd : sta start condition hold time 4000 600 250 ? ? ? ns 1.8v v cc 2.5v 2.5v v cc 5.5v 2.5v v cc 5.5v (24FC515 only) 7t su : sta start condition setup time 4700 600 250 ? ? ? ns 1.8v v cc 2.5v 2.5v v cc 5.5v 2.5v v cc 5.5v (24FC515 only) 8t hd : dat data input hold time 0 ? ns (note 2) 9t su : dat data input setup time 250 100 100 ? ? ? ns 1.8v v cc 2.5v 2.5v v cc 5.5v 2.5v v cc 5.5v (24FC515 only) 10 t su : sto stop condition setup time 4000 600 250 ? ? ? ns 1.8v v cc 2.5v 2.5v v cc 5.5v 2.5v v cc 5.5v (24FC515 only) 11 t su : wp wp setup time 4000 600 600 ? ? ? ns 1.8v v cc 2.5v 2.5v v cc 5.5v 2.5v v cc 5.5v (24FC515 only) 12 t hd : wp wp hold time 4700 1300 1300 ? ? ? ns 1.8v v cc 2.5v 2.5v v cc 5.5v 2.5v v cc 5.5v (24FC515 only) 13 t aa output valid from clock (note 2) ? ? ? 3500 900 400 ns 1.8v v cc 2.5v 2.5v v cc 5.5v 2.5v v cc 5.5v (24FC515 only) 14 t buf bus free time: time the bus must be free before a new transmission can start 4700 1300 500 ? ? ? ns 1.8v v cc 2.5v 2.5v v cc 5.5v 2.5v v cc 5.5v (24FC515 only) 15 t of output fall time from v ih minimum to v il maximum c b 100 pf 10 + 0.1c b 250 250 ns all except, 24FC515 (note 1) 24FC515 (note 1) 16 t sp input filter spike suppression (sda and scl pins) ? 50 ns all except, 24FC515 (notes 1 and 3) 17 t wc write cycle time (byte or page) ? 5 ms 18 endurance 1 m ? cycles 25c, v cc = 5.0v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt tri gger inputs which provi de improved noise spike suppression. this eliminates the need for a ti specification for standard operation. 4: this parameter is not tested but established by characteri zation. for endurance estimates in a specific application, please consult the total endurance? m odel which can be obtained from microchip?s web site @www.microchip.com.
24aa515/24lc515/24FC515 ds21673c-page 4 preliminary ? 2003 microchip technology inc. figure 1-1: bus timing data (unprotected) (protected) scl sda in sda out wp 5 7 6 16 3 2 89 13 d4 4 10 11 12 14
? 2003 microchip technology inc. preliminary ds21673c-page 5 24aa515/24lc515/24FC515 2.0 pin descriptions the descriptions of the pins are listed in table 2-1. table 2-1: pin function table 2.1 a0, a1 chip address inputs the a0, a1 inputs are used by the 24xx515 for multiple device operations. the levels on these inputs are compared with the corresponding bits in the slave address. the chip is selected if the compare is true. up to four devices may be connected to the same bus by using different chip select bit combinations. if left unconnected, these inputs will be pulled down internally to v ss . 2.2 a2 chip address input the a2 input is non-configurable chip select. this pin must be tied to v cc in order for this device to operate. 2.3 serial data (sda) this is a bidirectional pin used to transfer addresses and data into and data out of the device. it is an open- drain terminal, therefore, the sda bus requires a pull- up resistor to v cc (typical 10 k ? for 100 khz, 2 k ? for 400khz and 1mhz). for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 2.4 serial clock (scl) this input is used to synchronize the data transfer from and to the device. 2.5 write-protect (wp) this pin can be connected to either v ss , v cc or left floating. an internal pull-down resistor on this pin will keep this device in the unprotected state if left floating. if tied to v ss or left floating, normal memory operation is enabled (read/write the entire memory 0000h- ffffh). if tied to v cc , write operations are inhibited. read operations are not affected. 3.0 functional description the 24xx515 supports a bidirectional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. the bus must be controlled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions while the 24xx515 works as a slave. both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. name pdip soic function a0 1 1 user configurable chip select a1 2 2 user configurable chip select a2 3 3 non-configurable chip select. this pin must be hard wired to logical 1 state (v cc ). device will not operate with this pin left floating or held to logical 0 (v ss ). v ss 4 4 ground sda 5 5 serial data scl 6 6 serial clock wp 7 7 write-protect input v cc 8 8 +1.8 to 5.5v (24aa515) +2.5 to 5.5v (24lc515) +4.5 to 5.5v (24FC515)
24aa515/24lc515/24FC515 ds21673c-page 6 preliminary ? 2003 microchip technology inc. 4.0 bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 4-1). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must end with a stop condition. 4.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device. 4.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull-down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24xx515) will leave the data line high to enable the master to generate the stop condition. figure 4-1: data transfer sequence on the serial bus figure 4-2: acknowledge timing note: the 24xx515 does not generate any acknowledge bits if an internal program- ming cycle is in progress. address or acknowledge valid data allowed to change stop condition start condition scl sda (a) (b) (d) (d) (c) (a) scl 9 8 7 6 5 4 3 2 1123 transmitter must release the sda line at this point allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. data from transmitter data from transmitter sda acknowledge bit
? 2003 microchip technology inc. preliminary ds21673c-page 7 24aa515/24lc515/24FC515 5.0 device addressing a control byte is the first byte received following the start condition from the master device (figure 5-1). the control byte consists of a 4-bit control code; for the 24xx515, this is set as ? 1010 ? binary for read and write operations. the next bit of the control byte is the block select bit (b0). this bit acts as the a15 address bit for accessing the entire array. the next two bits of the control byte are the chip select bits (a1, a0). the chip select bits allow the use of up to four 24xx515 devices on the same bus and are used to select which device is accessed. the chip select bits in the control byte must correspond to the logic levels on the corresponding a1 and a0 pins for the device to respond. these bits are in effect the two most significant bits of the word address. the last bit of the control byte defines the operation to be performed. when set to a one, a read operation is selected, and when set to a zero, a write operation is selected. the next two bytes received define the address of the first data byte (figure 5-2). because only a14?a0 are used, the upper address bit is a don?t care. the upper address bits are transferred first, followed by the less significant bits. following the start condition, the 24xx515 monitors the sda bus checking the device type identifier being transmitted. upon receiving a ? 1010 ? code and appro- priate device select bits, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24xx515 will select a read or write operation. this device has an internal addressing boundary limitation that is divided into two segments of 256k bits. block select bit ?b0? is used in place of address bit location ?a15? to control access to each segment. figure 5-1: control byte format 5.1 contiguous addressing across multiple devices the chip select bits a1, a0 can be used to expand the contiguous address space for up to 2 mbit by adding up to four 24xx515's on the same bus. in this case, software can use a0 of the control byte as address bit a16 and a1 as address bit a17. it is not possible to sequentially read across device boundaries. each device has internal addressing boundary limitations. this divides each part into two segments of 256k bits. the block select bit ?b0? controls access to each ?half? rather than address bit location a15. sequential read operations are limited to 256k blocks. to read through four devices on the same bus, eight random read commands must be given. figure 5-2: address sequence bit assignments 1 0 1 0 b0 a1 a0 sack r/w control code chip select bits slave address acknowledge bit start bit read/write bit 1010 b 0 a 1 a 0 r/w x a 11 a 10 a 9 a 7 a 0 a 8 a 12 control byte address high byte address low byte control code chip select bits x = don?t care bit a 13 a 14 block select bit
24aa515/24lc515/24FC515 ds21673c-page 8 preliminary ? 2003 microchip technology inc. 6.0 write operations 6.1 byte write following the start condition from the master, the control code (four bits), the block select (one bit) the chip select (two bits), and the r/w bit (which is a logic low) are clocked onto the bus by the master transmitter. this indicates to the addressed slave receiver that the address high byte will follow after it has generated an acknowledge bit during the ninth clock cycle. there- fore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24xx515. the next byte is the least significant address byte. after receiving another acknowledge signal from the 24xx515, the master device will transmit the data word to be written into the addressed memory location. the 24xx515 acknowledges again and the master generates a stop condition. this initiates the internal write cycle and dur- ing this time, the 24xx515 will not generate acknowl- edge signals (figure 6-1). if an attempt is made to write to the array with the wp pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command. after a byte write command, the internal address counter will point to the address location following the one that was just written. 6.2 page write the write control byte, word address, and the first data byte are transmitted to the 24xx515 in the same way as in a byte write. but instead of generating a stop condition, the master transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. after receipt of each word, the six lower address pointer bits are internally incremented by one. if the master should transmit more than 64 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received, an internal write cycle will begin (figure 6-2). if an attempt is made to write to the array with the wp pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command. 6.3 write protection the wp pin allows the user to write-protect the entire array (0000-ffff) when the pin is tied to v cc . if tied to v ss or left floating, the write protection is disabled. the wp pin is sampled at the stop bit for every write command (figure 1-1) toggling the wp pin after the stop bit will have no effect on the execution of the write cycle. note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
? 2003 microchip technology inc. preliminary ds21673c-page 9 24aa515/24lc515/24FC515 figure 6-1: byte write figure 6-2: page write x bus activity master sda line bus activity s t a r t control byte address high byte address low byte data s t o p a c k a c k a c k a c k x = don?t care bit s1010 0 b 0 a 1 a 0 p x bus activity master sda line bus activity s t a r t control byte address high byte address low byte data byte 0 s t o p a c k a c k a c k a c k data byte 63 a c k x = don?t care bit s10 1 0 0 b 0 a 1 a 0 p
24aa515/24lc515/24FC515 ds21673c-page 10 preliminary ? 2003 microchip technology inc. 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput.) once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition, followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if no ack is returned, then the start bit and control byte must be resent. if the cycle is complete, then the device will return the ack, and the master can then proceed with the next read or write command. see figure 7-1 for flow diagram. figure 7-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes
? 2003 microchip technology inc. preliminary ds21673c-page 11 24aa515/24lc515/24FC515 8.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the control byte is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 8.1 current address read the 24xx515 contains an address counter that main- tains the address of the last word accessed, internally incremented by one. therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. upon receipt of the control byte with r/w bit set to one, the 24xx515 issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24xx515 discontinues transmission (figure 8-1). figure 8-1: current address read 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24xx515 as part of a write operation (r/w bit set to 0). after the word address is sent, the master generates a start condition following the acknowledge. this termi- nates the write operation, but not before the internal address pointer is set. then, the master issues the control byte again but with the r/w bit set to a one. the 24xx515 will then issue an acknowledge and transmit the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition which causes the 24xx515 to discontinue transmission (figure 8-2). after a random read command, the inter- nal address counter will point to the address location following the one that was just read. 8.3 sequential read sequential reads are initiated in the same way as a random read except that after the 24xx515 transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. this acknowledge directs the 24xx515 to trans- mit the next sequentially addressed 8-bit word (figure 8-3). following the final byte transmitted to the master, the master will not generate an acknowledge but will generate a stop condition. to provide sequen- tial reads, the 24xx515 contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows half the memory contents to be serially read during one opera- tion. sequential read address boundaries are 0000h to 7fffh and 8000h to ffffh. the internal address pointer will automatically roll over from address 7fff to address 0000 if the master acknowledges the byte received from the array address 7fff. the internal address counter will automatically roll over from address ffffh to address 8000h if the master acknowledges the byte received from the array address ffffh. bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k 11 00 baa 1 byte 010
24aa515/24lc515/24FC515 ds21673c-page 12 preliminary ? 2003 microchip technology inc. figure 8-2: random read figure 8-3: sequential read x bus activity master sda line bus activity a c k n o a c k a c k a c k a c k s t o p s t a r t control byte address high byte address low byte control byte data byte s t a r t x = don?t care bit s1010 baa 0 010 s1 01 0 baa 1 010 p bus activity master sda line bus activity control byte data n data n + 1 data n + 2 data n + x n o a c k a c k a c k a c k a c k s t o p p
? 2003 microchip technology inc. preliminary ds21673c-page 13 24aa515/24lc515/24FC515 9.0 packaging information 9.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard marking consists of microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). for marking beyond this, certain price adders apply. please 24lc515 i/pnnn yyww 8-lead soic (208 mil) example: xxxxxxxx yywwnnn xxxxxxxx 24lc515 yywwnnn i/sm
24aa515/24lc515/24FC515 ds21673c-page 14 preliminary ? 2003 microchip technology inc. 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
? 2003 microchip technology inc. preliminary ds21673c-page 15 24aa515/24lc515/24FC515 8-lead plastic small outline (sm) ? medium, 208 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.43 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.64 0.51 .030 .025 .020 l foot length 5.33 5.21 5.13 .210 .205 .202 d overall length 5.38 5.28 5.11 .212 .208 .201 e1 molded package width 8.26 7.95 7.62 .325 .313 .300 e overall width 0.25 0.13 0.05 .010 .005 .002 a1 standoff 1.98 .078 a2 molded package thickness 2.03 .080 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 a a1 l c 2 1 d n p b e e1 .070 .075 .069 .074 1.78 1.75 1.97 1.88 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. drawing no. c04-056 significant characteristic
24aa515/24lc515/24FC515 ds21673c-page 16 preliminary ? 2003 microchip technology inc. appendix a: revision history revision c corrections to section 1.0, electrical characteristics.
? 2003 microchip technology inc. preliminary ds21673c-page 17 24aa515/24lc515/24FC515 on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
24aa515/24lc515/24FC515 ds21673c-page 18 preliminary ? 2003 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21673c 24aa515/24lc515/24FC515 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2003 microchip technology inc. preliminary ds21673c-page 19 24aa515/24lc515/24FC515 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support data sheets products supported by a preliminary data sheet may have an e rrata sheet describing minor operational differences and recom- mended workarounds. to determine if an erra ta sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. x /xx package temperature range device device 24aa515: = 512k bit 1.8v i 2 c cmos serial eeprom 24aa515t: = 512k bit 1.8v i 2 c cmos serial eeprom (tape and reel) 24lc515: = 512k bit 2.5v i 2 c cmos serial eeprom 24lc515t: = 512k bit 2.5v i 2 c cmos serial eeprom (tape and reel) 24FC515: = 512k bit 2.5v i 2 c cmos serial eeprom 24FC515t: = 512k bit 2.5v i 2 c cmos serial eeprom (tape and reel) temperature range i = -40 c to +85 c package p = plastic dip (300 mil body), 8-lead sm = plastic soic (208 mil body), 8-lead examples: a) 24aa515t-i/sm: tape and reel, industrial temperature, soic package. b) 24lc515-i/p: industrial temperature, pdip package. c) 24lc515-i/sm: industrial temperature, soic package. d) 24lc515t-i/sm: tape and reel, industrial temperature, soic package.
24aa515/24lc515/24FC515 ds21673c-page 20 preliminary ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. preliminary ds21673c-page 21 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microc hip?s products as critical com- ponents in life support systems is not authorized except with express written approval by mi crochip. no licenses are con- veyed, implicitly or otherwis e, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of micr ochip technology incorporated in the u.s.a. application maestro, dspicdem, dspicdem.net, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smar ttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned he rein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are comm itted to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
ds21673c-page 22 preliminary ? 2003 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com atlanta 3780 mansell road, suite 130 alpharetta, ga 30022 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, in 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 phoenix 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-4338 san jose 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu rm. 2401-2402, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - hong kong sar unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen rm. 1812, 18/f, building a, united plaza no. 5022 binhe road, futian district shenzhen 518033, china tel: 86-755-82901380 fax: 86-755-8295-1393 china - shunde room 401, hongjian building no. 2 fengxiangnan road, ronggui town shunde city, guangdong 528303, china tel: 86-765-8395507 fax: 86-765-8395571 china - qingdao rm. b505a, fullhope plaza, no. 12 hong kong central rd. qingdao 266071, china tel: 86-532-5027355 fax: 86-532-5027205 india divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan kaohsiung branch 30f - 1 no. 8 min chuan 2nd road kaohsiung 806, taiwan tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe austria durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45-4420-9895 fax: 45-4420-9910 france parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy via quasimodo, 12 20025 legnano (mi) milan, italy tel: 39-0331-742611 fax: 39-0331-466781 netherlands p. a. de biesbosch 14 nl-5152 sc drunen, netherlands tel: 31-416-690399 fax: 31-416-690340 united kingdom 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-118-921-5869 fax: 44-118-921-5820 07/28/03 w orldwide s ales and s ervice

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